Less than two years after developing 7nm test chips with 20 billion transistors, the researchers say they have paved the way for 30 billion transistors on a fingernail-sized chip with quadruple all-around nanowire gates.
Scientists have been saying with more frequency that Moore's Law may be at, or at least near, its outer limits due to the limitations of physical science.
The most efficient silicon chips today are manufacturing using a technology called FinFET (fin field effect transistor) that uses thin, vertical silicon "fins" to improve electrical control in transistors. Two years ago it developed a 7nm process, but today the company announced an industry-first process for building 5nm chips. Not only that, but the 5nm chips also promise a 40% increase in performance or a 75% reduction in power consumption over the 10nm process technology now in use by Samsung.
To achieve the breakthrough the Research Alliance had to overcome the problems plaguing EUV (extreme ultraviolet) lithography, which was already on its roadmap for producing 7nm FinFETs. In some background information to the development, we are told that IBM has been exploring nanosheet semiconductor technology for more than 10 years.
Huiming Bu, IBM's director of silicon integration and device research, said that all this means transistors can be packed four times as densely on a chip compared with today's technology.
IBM Research believes the latest transistor process can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance.
IBM is presenting details of its research on its "silicon nanosheet transistors" at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design. However, it's also painting a rosy picture for the future of mobile devices - it imagines phones having "two to three times" more battery life than current devices.
Although FinFET processes can also be scaled down to 5nm, reducing the space between the fins doesn't increase the current flow for additional performance. The reduction in chip size has, however, seen to the further thinning out of the chips making the third dimension irrelevant.
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